JVL MAC050 User Manual page 447

6.12
Reg. Firmware / MacRegIo
Nr. Name
243 ERR_VALUE
246 ZUP2_BITS
253 BUILD_NO
254 FPGA_VERSION
255 COUNTER_100US
256 SAMPLE5
257 SAMPLE6
258 SAMPLE7
259 SAMPLE8
262 MB_RD_REG
264 MB_WR_REG
265 MB_WR_DATA
266 RXP_COMM_RES
JVL A/S - User Manual - Integrated Servo Motors MAC050 - 4500
Registers
MacTalk Size /
Name Access
0 Word/
N/A
RW
0 Word/RW
(not
present)
Na Word/RO
(not
present)
Na Word/RO
(not
present)
Na / Word /
(not
present) 0 RW
Na / Word /
(not
0 RW
present)
Na / Word /
(not
present) 0 RW
Na / Word /
(not
0 RW
present)
0 Word/
N/A
RO
0 WORD/
N/A
RO
0 WORD/
N/A
RO
(not
present)
Description
- NOTE: This is intended only for JVL technicians.
For some, but only some, values of ERR_INFO above, this register
gives more information n the error. For ERR_INFO values X, the value
Y in this register means:
0=No information.
1=FPGA hardware timer value for late writing > 833.
2=Number of encoder pulses over the last 100/200 us.
3=The single-turn encoder count that triggered the error.
4=The velocity measured, same scaling as V_IST.
5=The measured A current value in HW units (0..3200).
6=The measured B current value in HW units (0..3200).
7=The measured C current value in units of 13 mA.
8=Number of consecutive times the current was clipped.
9=Bitmask of FPGA encoder status register, including bits:
Bit-7:IndexDetectedThisPeriod
Bit-6:IndexDetectedTooEarly
Bit-5:ExpectedÍndexNotDetected.
10=Not used.
11=Flashed product version byte (0x10=v1.0).
12=Not used.
13+: reserved for future use.
- Individual bits enable options:
Bit 0: Option to modify the classic scope/sampling system to sample
only every other time.
Bit 1:Enable position capture to POS5 (P6) when ANINP2 is/rises
above +5.00 Volts
Bit 2:Enable position capture to CAPCOM5 when ANINP2 is/drops
below +5.00 Volts
Bit 3: Select edge trigged position capture for both ANINP1 And
ANINP2 functions when set to one. Select level triggered position
capture when cleared to zero.
Bits 7...4: Low-noise option. 0=most noise and strongest movement,
15 = lowest noise and weakest movement.
Bits 8 through 31: Reserved for future use – must be written as zero.
- Build number as a unique time stamp. The value reflects the time of
firmware compilation in seconds since the beginning of 1 January
1970. This is standard UNIX time.
- Version code of the FPGA image. Not valid for all motor types. Can be
used to verify if a firmware update completed successfully.
Free running counter that ticks every 100 us.
- SAMPLE5..8 controls the advanced scope/sample function.
Register number, bit field and min/max/average sample type for the
fifth value in each sample.
- Register number, bit field and min/max/average sample type for the
sixth value in each sample.
- Register number, bit field and min/max/average sample type for the
seventh value in each sample.
- Register number, bit field and min/max/average sample type for the
eight value in each sample.
- Last register number read over the Modbus interface. This is useful
mainly for monitoring values on the Scope/sampling system to get
accurate timing information between register read/write, I/O signals
and motor operation.
- Last register Number written over the Modbus interface. Note this only
shows single register writes – not the up to 8 cyclic register blocks
used by earlier versions of the Ethernet modules. See also register 262
above.
- Last register Value written over the Modbus interface. Note this only
shows single register writes – not the up to 8 cyclic register blocks
used by earlier versions of the Ethernet modules. See also register 262
above.
- Result of the presently executing or latest executed communications
operation ordered from the eRxP system.
0=Idle – last operation completed successfully.
1=Busy – execution in progress, and hasn't yet timed out or used all
retries.
2= Failure – last operation could not be completed even after using all
retries.
Only MAC400 to 4500
st
TT15 56 -02GB
443