JVL MAC050 User Manual page 429

6.12
Reg. Firmware /
Nr. MacRegIo Name
39 HW_SETUP
JVL A/S - User Manual - Integrated Servo Motors MAC050 - 4500
Registers
MacTalk Size /
Name Access
Na / Word /
(not present)
9 RW
Description
- Bit 0, DIRAWR
Bit 1, DIRBWR
Selects the basic functions of Pulse In, Serial Data and Pulse out on the
Multi-Function RS422 interface 1 (MF1).
DIRAWR=0, DIRBWR=0: Pulse-In mode.
DIRAWR=1, DIRBWR=1: Pulse-Out mode.
DIRAWR=1, DIRBWR=0: Serial interface mode.
DIRAWR=0, DIRBWR=2: User defined switchboard /'crossfield' setup for
MF1/MF2 signals. This can be configured via Reg230/231 index/data
registers, and is only used for special applications.
PulseIn and PulseOut are used mainly for applications where two motors
follow the same encoder, possibly with a gearing ratio (in firmware).
PulseIn will allow the motor to follow a foreign encoder signal, while
PulseOut will output the motors own encoder signals for a foreign motor to
follow it.
Bit 2, PULSEOUT
Must also be set to support encoder Pulse-Out on the RS422 interface
(MF1).
Bit 3, XSEL1
Selects if external encoder pulses are received from the MF1 (0) or MF2
(1) electrical RS422 interfaces.
Bit 4, XPRINP
Select encoder external encoder data format Pulse/Direction (1) or
Quadrature input type (0).
Bit 5, NOFILT
Disable low-pass filtering of external encoder pulses.
Bit 6, INVXDIR
Invert the counting direction for incoming encoder pulses from an external
encoder when in Pulse-In mode.
Bit 7, INVROTDIR
Inverts the logical motor directions from CW to CCW. This works for
velocity, position and gear modes.
Bit 8, USER_INPOS
Selects if hardware signals OUT1 should be used for standard InPosition
and ErrorOut signals (0), or be controlled by the lowest bit in register 207,
USER_OUT (1).
Bit 9, USER_ERROR
Error output pin OUT2 is controlled by the user via Reg207, USER_OUT
bit 1.
Bit 10, INV_INPOS_OUT
Bit 11, INV_ERROR_OUT
Bits 10 and 11 can be set individually to invert the logical state of the
InPosition(OUT1) and ErrorOut(OUT2) hardware signals. When the bit is
set, a signal will be active low instead of normally active high (PNP-
output). Note that this inversion is not active when the ouputs are user
controlled by bits 8 and 9 in this register.
Bit 12, CMP_ERROR_OUT
If set, OUT2_PIN is controlled by (P_IST > CMP_POS0)
(continued next page)
Only MAC400 to 4500
T1507-02GB
425