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20.4.1
A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■ A/D Control Status Register 1 (ADCS1)
bit
Address
000035
H
: Read/write
R/W
W
: Write only
: Undefined
-
: Initial value
Figure 20.4-2 A/D Control Status Register 1 (ADCS1)
15
14
13
12
11
BUSY
INT
INTE
PAUS
STS1
R/W
R/W
R/W
R/W
R/W
INT
A/D conversion is halt.
CHAPTER 20 8/10-BIT A/D CONVERTER
10
9
8
7
STRT RESV
STS0
(ADCS0)
R/W
W
R/W
RESV
Always write 0 to this bit
A/D conversion activation bit
STRT
(
valid only when activated by software (ADC2: EXT= 0))
Does not activate the A/D conversion
0
Activate the A/D conversion function
1
STS1 STS0
A/D activation select bit
0
0
Activation by software
0
1
Activation by external trigger or software
1
0
Activation by timer or software
Activation by external trigger, timer, or
1
1
software
PAUS
(valid only when EI
0
A/D conversion is not halted
A/D conversion is halted
1
INTE
Interrupt request enable bit
0
Disables interrupt request output
1
Enables interrupt request output
Interrupt request flag bit
Read
0
A/D conversion has not been completed
1
A/D conversion has been completed
Busy bit
BUSY
Read
0
A/D conveision is halted
1
A/D conversion is in progress
0
Initial value
00000000
B
Reserved bit
Halt flag bit
2
OS is used)
Write
Clears this bit
No effect
Write
Stops the A/D conversion
No effect
549
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