Memory Architecture - Xilinx MicroBlaze Reference Manual

Memory Architecture

MicroBlaze is implemented with a Harvard memory architecture; instruction and data accesses are
done in separate address spaces. Each address space has a 32-bit range (that is, handles up to 4-GB
of instructions and data memory respectively). The instruction and data memory ranges can be made
to overlap by mapping them both to the same physical memory. The latter is useful for software
debugging.
Both instruction and data interfaces of MicroBlaze are default 32 bits wide and use big endian or
little endian, bit-reversed format, depending on the parameter C_ENDIANNESS. MicroBlaze
supports word, halfword, and byte accesses to data memory.
Data accesses must be aligned (word accesses must be on word boundaries, halfword on halfword
boundaries), unless the processor is configured to support unaligned exceptions. All instruction
accesses must be word aligned.
MicroBlaze prefetches instructions to improve performance, using the instruction prefetch buffer
and (if enabled) instruction cache streams. To avoid attempts to prefetch instructions beyond the end
of physical memory, which may cause an instruction bus error or a processor stall, instructions must
not be located too close to the end of physical memory. The instruction prefetch buffer requires 16
bytes margin, and using instruction cache streams adds two additional cache lines (32 or 64 bytes).
MicroBlaze does not separate data accesses to I/O and memory (it uses memory mapped I/O). The
processor has up to three interfaces for memory accesses:
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The LMB memory address range must not overlap with AXI4, PLB or XCL ranges.
The C_ENDIANNESS parameter is automatically set to little endian when using AXI4, and to big
endian when using PLB, but can be overridden by the user.
MicroBlaze has a single cycle latency for accesses to local memory (LMB) and for cache read hits,
except with C_AREA_OPTIMIZED set to 1, when data side accesses and data cache read hits
require two clock cycles, and with C_FAULT_TOLERANT set to 1, when byte writes and halfword
writes to LMB normally require two clock cycles.
The data cache write latency depends on C_DCACHE_USE_WRITEBACK. When
C_DCACHE_USE_WRITEBACK is set to 1, the write latency normally is one cycle (more if the
cache needs to do memory accesses). When C_DCACHE_USE_WRITEBACK is cleared to 0, the
write latency normally is two cycles (more if the posted-write buffer in the memory controller is
full).
The MicroBlaze instruction and data caches can be configured to use 4 or 8 word cache lines. When
using a longer cache line, more bytes are prefetched, which generally improves performance for
software with sequential access patterns. However, for software with a more random access pattern
the performance can instead decrease for a given cache size. This is caused by a reduced cache hit
rate due to fewer available cache lines.
For details on the different memory interfaces refer to
Description.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Local Memory Bus (LMB)
Advanced eXtensible Interface (AXI4) or Processor Local Bus (PLB)
Advanced eXtensible Interface (AXI4) or Xilinx CacheLink (XCL)
www.xilinx.com
Memory Architecture
Chapter 3, MicroBlaze Signal Interface
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