Clock Source - ST STM32F205 series Reference Manual

RM0033
Figure 189. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
Update interrupt flag (UIF)
Figure 190. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
16.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 191
without prescaler.
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Auto-reload register
Write a new value in TIMx_ARR
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Write a new value in TIMx_ARR
shows the behavior of the control circuit and the upcounter in normal mode,
preloaded)
31 32 33 34 35 36 00
FF
preloaded)
F0 F1 F2 F3 F4 F5 00
F5
F5
RM0033 Rev 8
Basic timers (TIM6 and TIM7)
01 02 03 04 05 06 07
36
01 02 03 04 05 06 07
36
36
MSv37303V1
MSv37304V1
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