Hash Digest Registers (Hash_Hr0 - ST STM32F205 series Reference Manual

Hash processor (HASH)
21.4.4

HASH digest registers (HASH_HR0..4)

Address offset: 0x0C to 0x1C
Reset value: 0x0000 0000
These registers contain the message digest result named as:
1. H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description
2. A, B, C and D, respectively, in the MD5 algorithm description
Note that in this case, the HASH_H4 is not used, and is read as
3. H0 to H6, respectively, in the SHA224 algorithm description,
4. H0 to H7, respectively, in the SHA256 algorithm description,
If a read access to one of these registers occurs while the HASH core is calculating an
intermediate digest or a final message digest (that is when the DCAL bit has been written to
1), then the read is stalled until the completion of the HASH calculation.
HASH_HR0
Address offset: 0x0C
31 30 29
r r r
15 14 13
r r r
HASH_HR1
Address offset: 0x10
31 30 29
r r r
15 14 13
r r r
HASH_HR2
Address offset: 0x14
31 30 29
r r r
15 14 13
r r r
HASH_HR3
Address offset: 0x18
564/1378
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
24 23 22
H0
r r r
8 7 6
H0
r r r
24 23 22
H1
r r r
8 7 6
H1
r r r
24 23 22
H2
r r r
8 7 6
H2
r r r
RM0033 Rev 8
zero.
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0033
17 16
r r
1 0
r r
17 16
r r
1 0
r r
17 16
r r
1 0
r r