RM0033
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
MII_CS
MII_COL
Figure 328
MII_RX_CLK
MII_TX_EN
MII_TXD[3:0]
RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
28.5.3
MAC frame reception
The MAC received frames are pushes into the Rx FIFO. The status (fill level) of this FIFO is
indicated to the DMA once it crosses the configured receive threshold (RTC in the
ETH_DMAOMR register) so that the DMA can initiate pre-configured burst transfers
towards the AHB interface.
In the default Cut-through mode, when 64 bytes (configured with the RTC bits in the
ETH_DMAOMR register) or a full packet of data are received into the FIFO, the data are
popped out and the DMA is notified of its availability. Once the DMA has initiated the
transfer to the AHB interface, the data transfer continues from the FIFO until a complete
Ethernet (ETH): media access control (MAC) with DMA controller
Figure 327. Transmission with collision
PR
EAM
shows a frame transmission in MII and RMII.
Figure 328. Frame transmission in MMI and RMII modes
RM0033 Rev 8
BLE
SFD
DA
DA
JAM
JAM
JAM
JAM
ai15651
ai15652
861/1378
957
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