Peripheral Fifo Architecture; Peripheral Rx Fifo; Figure 355. Device-Mode Fifo Address Mapping And Ahb Fifo Access Mapping - ST STM32F205 series Reference Manual

RM0033
29.11

Peripheral FIFO architecture

Figure 355. Device-mode FIFO address mapping and AHB FIFO access mapping

IN endpoint Tx FIFO #n
IN endpoint Tx FIFO #1
IN endpoint Tx FIFO #0
DFIFO push access
Any OUT endpoint DFIFO pop
29.11.1

Peripheral Rx FIFO

The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT
endpoints. Received packets are stacked back-to-back until free space is available in the
Rx-FIFO. The status of the received packet (which contains the OUT endpoint destination
number, the byte count, the data PID and the validity of the received data) is also stored by
the core on top of the data payload. When no more space is available, host transactions are
NACKed and an interrupt is received on the addressed endpoint. The size of the receive
FIFO is configured in the receive FIFO Size register (GRXFSIZ).
The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in
the receive RAM buffer:
•
All OUT endpoints share the same RAM buffer (shared FIFO)
• The OTG FS core can fill in the receive FIFO up to the limit for any host sequence of
OUT tokens
The application keeps receiving the Rx-FIFO non-empty interrupt (RXFLVL bit in
OTG_FS_GINTSTS) as long as there is at least one packet available for download. It reads
the packet information from the receive status read and pop register (GRXSTSP) and finally
pops data off the receive FIFO by reading from the endpoint-related pop address.
DFIFO push access
from AHB
MAC pop
DFIFO push access
from AHB
MAC pop
from AHB
MAC pop
access from AHB
MAC push
Dedicated Tx
FIFO #n control
(optional)
. .
.
Dedicated Tx
FIFO #1 control
(optional)
Dedicated Tx
FIFO #0 control
(optional)
Rx FIFO control
RM0033 Rev 8
USB on-the-go full-speed (OTG_FS)
Single data
FIFO
DIEPTXF2[31:16]
Tx FIFO #n
packet
DIEPTXFx[15:0]
. .
.
DIEPTXF2[15:0]
Tx FIFO #1 packet
DIEPTXF1[31:16]
DIEPTXF1[15:0]
Tx FIFO #0 packet GNPTXFSIZ[31:16]
GNPTXFSIZ[15:0]
GRXFSIZ[31:16]
Rx packets
A1 = 0
. .
.
(Rx start
address
fixed to 0)
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