Figure 220. Transfer Sequence Diagram For Master Transmitter - ST STM32F205 series Reference Manual

RM0033

Figure 220. Transfer sequence diagram for master transmitter

7-bit master transmitter
S Address A
EV5 EV6 EV8_1
10-bit master transmitter
S Header A
EV5 EV9
Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge,
r
EVx= Event (with interrupt if ITEVFEN = 1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.
EV8_1: TxE=1, shift register empty, data register empty, write Data1 in DR.
EV8: TxE=1, shift register not empty, data register empty, cleared by writing DR register
EV8_2: TxE=1, BTF = 1, Program Stop request. TxE and BTF are cleared by hardware by the Stop condition
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.
1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence.
2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission.
Data1 A Data2
EV8 EV8
Address A
EV6 EV8_1
.
RM0033 Rev 8
Inter-integrated circuit (I2C) interface
A
.....
EV8
Data1 A
.....
EV8 EV8
DataN A P
EV8_2
DataN A P
EV8_2
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