ST STM32F205 series Reference Manual page 131

RM0033
Bit 27 PORRSTF: POR/PDR reset flag
Bit 26 PINRSTF: PIN reset flag
Bit 25 BORRSTF: BOR reset flag
Bit 24 RMVF: Remove reset flag
Bits 23:2
Bit 1 LSIRDY: Internal low-speed oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Cleared by software by writing the RMVF bit.
Set by hardware when a POR/PDR or BOR reset occurs.
0: No POR/PDR or BOR reset occurred
1: POR/PDR or BOR reset occurred
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Reserved, always read as 0.
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.
0: LSI RC oscillator not ready
1: LSI RC oscillator ready
Set and cleared by software.
0: LSI RC oscillator OFF
1: LSI RC oscillator ON
RM0033 Rev 8
Reset and clock control (RCC)
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