Figure 343. Enhanced Transmit Descriptor - ST STM32F205 series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
TDES 0
TDES 1
TDES 2
TDES 3
TDES 4
TDES 5
TDES 6
TDES 7
•
TDES4: Transmit descriptor Word4
Reserved
•
TDES5: Transmit descriptor Word5
Reserved
•
TDES6: Transmit descriptor Word6
31 30 29 28 27 26 25
Bits 31:0 TTSL: Transmit frame time stamp low
This field is updated by DMA with the 32 least significant bits of the time stamp captured
for the corresponding transmit frame. This field has the time stamp only if the Last segment
control bit (LS) in the descriptor is set.
894/1378

Figure 343. Enhanced transmit descriptor

31
T
O
Ctrl Res.
T
W
[30:26] 24
S
N
E
Reserved Buffer 2 byte count
[31:29]
Buffer 2 address [31:0] or Next descriptor address [31:0]
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RM0033 Rev 8
T
Ctrl Reserved
T
[23:20] [19:18]
S
S
Reserved
[28:16] [15:13]
Buffer 1 address [31:0]
Reserved
Reserved
Time stamp low [31:0]
Time stamp high [31:0]
TTSL
rw
0
Status [16:0]
Buffer 1 byte count
[12:0]
ai17105b
9 8 7 6 5 4 3 2
RM0033
1 0