Figure 127. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6; Figure 128. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F205 series Reference Manual

General-purpose timers (TIM2 to TIM5)
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 127. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

Update interrupt flag (UIF)
1. Here, center-aligned mode 1 is used, for more details refer to
386/1378
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Counter overflow
Update event (UEV)

Figure 128. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
04 03 02 01 00 01
Section 14.4.1: TIMx control register 1 (TIMx_CR1)
0003 0002 0001
RM0033 Rev 8
02 03 04 05 06 05 04
0000 0001 0002 0003
RM0033
03
MS37342V1
.
MS37343V1