Timx Register Map; Table 62. Tim2 To Tim5 Register Map And Reset Values - ST STM32F205 series Reference Manual

RM0033
14.4.21

TIMx register map

TIMx registers are mapped as described in the table below:
Offset Register
TIMx_CR1
0x00
Reset value
TIMx_CR2
0x04
Reset value
TIMx_SMCR
0x08
Reset value
TIMx_DIER
0x0C
Reset value
TIMx_SR
0x10
Reset value
TIMx_EGR
0x14
Reset value
TIMx_CCMR1
Output Compare
mode
Reset value
0x18
TIMx_CCMR1
Input Capture
mode
Reset value
TIMx_CCMR2
Output Compare
mode
Reset value
0x1C
TIMx_CCMR2
Input Capture
mode
Reset value
TIMx_CCER
0x20
Reset value
TIMx_CNT
0x24
Reset value
TIMx_PSC
0x28
Reset value

Table 62. TIM2 to TIM5 register map and reset values

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CNT[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
General-purpose timers (TIM2 to TIM5)
Reserved
Reserved
ETPS
[1:0]
0 0 0
0 0
Reserved
OC2M
[2:0]
0 0 0
IC2F[3:0]
0 0 0
OC4M
[2:0]
0 0 0
IC4F[3:0]
0 0 0
0 0
0 0 0
0 0 0
RM0033 Rev 8
CKD CMS
[1:0] [1:0]
0 0 0 0 0
MMS[2:0]
0 0 0
ETF[3:0] TS[2:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
0
CC2S OC1M
[1:0] [2:0]
0 0 0 0 0 0 0 0
IC2
CC2S
PSC IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
CC4S OC3M
[1:0] [2:0]
0 0 0 0 0 0 0 0
IC4
CC4S
PSC IC3F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0
Reserved
0 0
SMS[2:0]
0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
CC1S
[1:0]
0 0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0 0
CC3S
[1:0]
0 0 0 0 0
IC3
CC3S
PSC
[1:0]
[1:0]
0 0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
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