Cryp Raw Interrupt Status Register (Cryp_Risr); Cryp Masked Interrupt Status Register (Cryp_Misr) - ST STM32F205 series Reference Manual

Cryptographic processor (CRYP)
19.6.7

CRYP raw interrupt status register (CRYP_RISR)

Address offset: 0x18
Reset value: 0x0000 0001
The CRYP_RISR register is the raw interrupt status register. It is a read-only register. On a
read, this register gives the current raw status of the corresponding interrupt prior to
masking. A write has no effect.
31 30 29
15 14 13
Bits 31:2 Reserved, must be kept at reset value
19.6.8

CRYP masked interrupt status register (CRYP_MISR)

Address offset: 0x1C
Reset value: 0x0000 0000
The CRYP_MISR register is the masked interrupt status register. It is a read-only register.
On a read, this register gives the current masked status of the corresponding interrupt prior
to masking. A write has no effect.
31 30 29
15 14 13
538/1378
28 27 26 25
12 11 10 9
Reserved
Bit 1 OUTRIS: Output FIFO service raw interrupt status
Gives the raw interrupt state prior to masking of the output FIFO service
interrupt.
0: Raw interrupt not pending
1: Raw interrupt pending
Bit 0 INRIS: Input FIFO service raw interrupt status
Gives the raw interrupt state prior to masking of the Input FIFO service interrupt.
0: Raw interrupt not pending
1: Raw interrupt pending
28 27 26 25
12 11 10 9
Reserved
24 23 22 21
Reserved
8 7 6
24 23 22
Reserved
8 7 6
RM0033 Rev 8
20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
RM0033
17 16
1 0
OUTRIS INRIS
r r
17 16
1 0
OUTMIS INMIS
r r