ST STM32F205 series Reference Manual page 815

RM0033
Bit 0 INRQ
CAN master status register (CAN_MSR)
Address offset: 0x04
Reset value: 0x0000 0C02
31 30 29
15 14 13
Reserved.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 RX
Bit 10 SAMP
Bit 9 RXM
Bit 8 TXM
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SLAKI
Note: When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can be
Bit 3 WKUI
:
Initialization request
The software clears this bit to switch the hardware into normal mode. Once 11 consecutive
recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and
ready for transmission and reception. Hardware signals this event by clearing the INAK bit in
the CAN_MSR register.
Software sets this bit to request the CAN hardware to enter initialization mode. Once
software has set the INRQ bit, the CAN hardware waits until the current CAN activity
(transmission or reception) is completed before entering the initialization mode. Hardware
signals this event by setting the INAK bit in the CAN_MSR register.
28 27 26 25
12 11 10 9
RX SAMP RXM
r r r
:
CAN Rx signal
Monitors the actual value of the CAN_RX Pin.
:
Last sample point
The value of RX on the last sample point (current received bit value).
:
Receive mode
The CAN hardware is currently receiver.
:
Transmit mode
The CAN hardware is currently transmitter.
:
Sleep acknowledge interrupt
When SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep
Mode. When set, this bit generates a status change interrupt if the SLKIE bit in the
CAN_IER register is set.
This bit is cleared by software or by hardware, when SLAK is cleared.
polled.
:
Wakeup interrupt
This bit is set by hardware to signal that a SOF bit has been detected while the CAN
hardware was in Sleep mode. Setting this bit generates a status change interrupt if the
WKUIE bit in the CAN_IER register is set.
This bit is cleared by software.
24 23 22
Reserved
8 7 6
TXM
Reserved
r
RM0033 Rev 8
Controller area network (bxCAN)
21 20 19 18
5 4 3 2
SLAKI WKUI ERRI
rc_w1 rc_w1 rc_w1
17 16
1 0
SLAK INAK
r r
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