ST STM32F205 series Reference Manual page 900

Ethernet (ETH): media access control (MAC) with DMA controller
Bit 5 FT: Frame type
When set, this bit indicates that the Receive frame is an Ethernet-type frame (the LT field is greater
than or equal to 0x0600). When this bit is reset, it indicates that the received frame is an
IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes. When the normal
descriptor format is used (ETH_DMABMR EDFE=0), FT can take on special meaning as
specified in
Bit 4 RWT: Receive watchdog timeout
When set, this bit indicates that the Receive watchdog timer has expired while receiving the
current frame and the current frame is truncated after the watchdog timeout.
Bit 3 RE: Receive error
When set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted
during frame reception.
Bit 2 DE: Dribble bit error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd
nibbles). This bit is valid only in MII mode.
Bit 1 CE: CRC error
When set, this bit indicates that a cyclic redundancy check (CRC) error occurred on the
received frame. This field is valid only when the last descriptor (RDES0[8]) is set.
Bit 0 PCE/ESA: Payload checksum error / extended status available
When set, it indicates that the TCP, UDP or ICMP checksum the core calculated does not
match the received encapsulated TCP, UDP or ICMP segment's Checksum field. This bit is
also set when the received number of payload bytes does not match the value indicated in
the Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame.
This bit can take on special meaning as specified in
If the enhanced descriptor format is enabled (EDFE=1, bit 7 in ETH_DMABMR), this bit takes
on the ESA function (otherwise it is PCE). When ESA is set, it indicates that the extended
status is available in descriptor word 4 (RDES4). ESA is valid only when the last descriptor bit
(RDES0[8]) is set.
Bits 5, 7, and 0 reflect the conditions discussed in
900/1378
Table 146.
RM0033 Rev 8
Table 146.
Table 146.
RM0033