Figure 65. Advanced-Control Timer Block Diagram - ST STM32F205 series Reference Manual

RM0033
CK_TIM18 from RCC
ETR
Polarity selection,
Edge detector and Prescaler
ITR0
ITR1
ITR2
ITR3
TI1
Input filter &
Edge detector
TI2
Input filter &
Edge detector
TI3
Input filter &
Edge detector
TI4
Input filter &
Edge detector
BRK
Polarity selection
Clock failure event from clock controller
CSS (Clock Security System)
Legend
Reg

Figure 65. Advanced-control timer block diagram

Internal clock (CK_INT)
ETRF
ETRP
Input filter
TGI
TRGI
TIF_ED
TI1FP1
TI2FP2
CK_PSC
TI1FP1
IC1
TI1FP2
TRC
TI2FP1
IC2
TI2FP2
TRC
TI3FP3
IC3
TI3FP4
TRC
TI4FP3
IC4
TI4FP4
TRC
Interrupt & DMA output
Preload registers transferred to active registers on U event according to control bit
Advanced-control timers (TIM1 and TIM8)
Trigger
controller
Slave mode
controller
Reset,
Enable,
Up/Down,
Count
Encoder
interface
AutoReload
U
Register
CK_CNT
PSC CNT
(prescaler) (counter)
CC4I
IC1PS
Capture/Compare
Prescaler
1 Register
U U
CC3I
IC2PS
Capture/Compare
Prescaler
2 Register
U
CC2I
IC3PS
Capture/Compare
Prescaler
3 Register
U
CC1I
IC4PS
Capture/Compare
Prescaler
4 Register
U
BI
Event
RM0033 Rev 8
TRGO To other timers
To DAC and ADC
REP Register
Repetition counter
DTG[7:0] registers
CC4I
OC1REF
CC3I
OC2REF
CC2I
OC3REF
CC1I
OC4REF
DTG Output control
UI
U
OC2N
OC3
OC4
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