ST STM32F205 series Reference Manual page 96

Advanced arm-based 32-bit mcus
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Reset and clock control (RCC)
Bit 18 HSEBYP: HSE clock bypass
Bit 17 HSERDY: HSE clock ready flag
Bit 16 HSEON: HSE clock enable
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
Bit 2
Bit 1 HSIRDY: Internal high-speed clock ready flag
Bit 0 HSION: Internal high-speed clock enable
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Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,
HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
These bits are initialized automatically at startup.
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to
16 MHz ± 1%. The typical trimming step (F
is around 80 kHz.
Reserved, always read as 0.
Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in
case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit
cannot be cleared if the HSI is used directly or indirectly as the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON
) between two consecutive HSICAL steps
HSITRIM
RM0033 Rev 8
RM0033

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