Debug Mode; Table 71. Table - ST STM32F205 series Reference Manual

Window watchdog (WWDG)
As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3
and T[5:0] is set to 63:
Refer to
Prescaler
1
2
4
8
18.5

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_WWDG_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and I
504/1378
t WWDG = 1
Table 71 for the minimum and maximum values of the t
Table 71. Minimum and maximum timeout values at 30 MHz (f
WDGTB
0
1
2
3
3
⁄ × ×
24000 4096 2
Min timeout (µs)
T[5:0] = 0x00
136.53
273.07
546.13
1092.27
2
C.
RM0033 Rev 8
× ( )
63 + 1 = 21.85ms
.
WWDG
Max timeout (ms)
T[5:0] = 0x3F
8.74
17.48
34.95
69.91
®
-M3 core halted), the WWDG counter
Section 32.16.2: Debug support
RM0033
)
PCLK1