Figure 79. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6; Figure 80. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F205 series Reference Manual

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When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The repetition counter is reloaded with the content of TIMx_RCR register
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 79. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

1.
Here, center-aligned mode 1 is used (for more details refer to
CK_PSC
CEN
Timerclock = CK_CNT
Counter register
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 80. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Advanced-control timers (TIM1 and TIM8)
04 03 02 01 00 01
Section 13.4: TIM1 and TIM8
0003 0002 0001
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02 03 04 05 06 05 04
registers).
0000 0001 0002 0003
03
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