Tim1 And Tim8 Dma/Interrupt Enable Register (Timx_Dier); Table 56. Timx Internal Trigger Connection - ST STM32F205 series Reference Manual

Advanced-control timers (TIM1 and TIM8)
Bits 2:0 SMS: Slave mode selection
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
Slave TIM
TIM1
TIM8
13.4.4

TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
TDE COMDE CC4DE CC3DE CC2DE CC1DE
Res.
rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
Bit 13 COMDE: COM DMA request enable
354/1378
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
The clock of the slave timer must be enabled prior to receiving events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 56. TIMx Internal trigger connection

ITR0 (TS = 000)
TIM5_TRGO
TIM1_TRGO
12 11 10 9
rw rw rw rw
0: Trigger DMA request disabled
1: Trigger DMA request enabled
0: COM DMA request disabled
1: COM DMA request enabled
ITR1 (TS = 001)
TIM2_TRGO
TIM2_TRGO
8 7 6
UDE BIE TIE COMIE CC4IE
rw rw rw
RM0033 Rev 8
ITR2 (TS = 010) ITR3 (TS = 011)
TIM3_TRGO
TIM4_TRGO
5 4 3 2
CC3IE CC2IE
rw rw rw rw
RM0033
TIM4_TRGO
TIM5_TRGO
1 0
CC1IE UIE
rw rw