Dynamic Update Of The Otg_Fs_Hfir Register - ST STM32F205 series Reference Manual

RM0033
The power consumption of the OTG PHY is controlled by three bits in the general core
configuration register:
•
PHY power down (GCCFG/PWRDWN)
It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily
set to allow any USB operation.
•
A-V
It switches on/off the V
be set when in A-device (USB host) mode and during HNP.
•
B-V
It switches on/off the V
be set when in B-device (USB peripheral) mode and during HNP.
Power reduction techniques are available while in the USB suspended state, when the USB
session is not yet valid or the device is disconnected.
•
Stop PHY clock (STPPCLK bit in OTG_FS_PCGCCTL)
When setting the stop PHY clock bit in the clock gating control register, most of the
48 MHz clock domain internal to the OTG full-speed core is switched off by clock
gating. The dynamic power consumption due to the USB clock switching activity is cut
even if the 48 MHz clock input is kept running by the application
Most of the transceiver is also disabled, and only the part in charge of detecting the
asynchronous resume or remote wakeup event is kept alive.
• Gate HCLK (GATEHCLK bit in OTG_FS_PCGCCTL)
When setting the Gate HCLK bit in the clock gating control register, most of the system
clock domain internal to the OTG_FS core is switched off by clock gating. Only the
register read and write interface is kept alive. The dynamic power consumption due to
the USB clock switching activity is cut even if the system clock is kept running by the
application for other purposes.
•
USB system stop
When the OTG_FS is in the USB suspended state, the application may decide to
drastically reduce the overall power consumption by a complete shut down of all the
clock sources in the system. USB System Stop is activated by first setting the Stop
PHY clock bit and then configuring the system deep sleep mode in the power control
system module (PWR).
The OTG_FS core automatically reactivates both system and USB clocks by
asynchronous detection of remote wakeup (as an host) or resume (as a device)
signaling on the USB.
To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS
core.
29.9

Dynamic update of the OTG_FS_HFIR register

The USB core embeds a dynamic trimming capability of SOF framing period in host mode
allowing to synchronize an external device with the SOF frames.
When the OTG_FS_HFIR register is changed within a current SOF frame, the SOF period
correction is applied in the next frame as described in
sensing enable (GCCFG/VBUSASEN)
BUS
BUS
sensing enable (GCCFG/VBUSASEN)
BUS
BUS
USB on-the-go full-speed (OTG_FS)
comparators associated with A-device operations. It must
comparators associated with B-device operations. It must
RM0033 Rev 8
Figure 354.
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