Cryp Busy State; Figure 208. Initialization Vectors Use In The Tdes-Cbc Encryption - ST STM32F205 series Reference Manual

Cryptographic processor (CRYP)
bit string
19.3.5

CRYP busy state

When there is enough data in the input FIFO (at least 2 words for the DES or TDES
algorithm mode, 4 words for the AES algorithm mode) and enough free-space in the output
FIFO (at least 2 (DES/TDES) or 4 (AES) word locations), and when the bit CRYPEN = 1 in
the CRYP_CR register, then the cryptographic processor automatically starts an encryption
or decryption process (according to the value of the ALGODIR bit in the CRYP_CR
register).
This process takes 48 AHB2 clock cycles for the Triple-DES algorithm, 16 AHB2 clock
cycles for the simple DES algorithm, and 14, 16 or 18 AHB2 clock cycles for the AES with
key lengths of 128, 192 or 256 bits, respectively. During the whole process, the BUSY bit in
the CRYP_SR register is set to '1'. At the end of the process, two (DES/TDES) or four (AES)
words are written by the CRYP Core into the output FIFO, and the BUSY bit is cleared. In
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Figure 208. Initialization vectors use in the TDES-CBC encryption

TDES-CBC en cryption ex ample, DATATYPE = 11b
bit 31 bit 30 bit 2 bit 1
bit 31 bit 30 bit 2 bit 1
M1 M2 M30 M31 M32
CRYP_IVL
31 30 2 1
IV1 IV2 IV30 IV31 IV32 IV33 IV34
I1 I2 I30 I31 I32
DEA Encrypt,
DEA Decrypt,
DEA Encrypt,
CRYP_IVL
31 30 2 1
IV1 IV2 IV30 IV31 IV32 IV33 IV34
OUT FIFO
First word from the OUT FIFO contains the left part of the cyphertext block (O1...32)
Second word from OUT FIFO contains the right part of cyphertext block (O33...64)
second word written into the CRYP_DIN register
bit 0
bit 0
first word written into the CRYP_DIN register
M33 M34 M62 M63 M64
CRYP_IVR
0 31 30 2
IV62 IV63 IV64
I33 I34 I62 I63 I64
K1
K2
K3
CRYP_IVR
0 31 30 2
IV62 IV63 IV64
RM0033 Rev 8
1 0
1 0
CRYP result is copied
back to the CRYP_IVL/R
registers after cyphering
RM0033
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