ST STM32F205 series Reference Manual page 128

Reset and clock control (RCC)
Bit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode
Bit 9 ADC2LPEN: ADC2 clock enable during Sleep mode
Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode
Bits 7:6
Bit 5 USART6LPEN: USART6 clock enable during Sleep mode
Bit 4 USART1LPEN: USART1 clock enable during Sleep mode
Bits 3:2
Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode
Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode
128/1378
Set and cleared by software.
0: ADC 3 clock disabled during Sleep mode
1: ADC 3 clock disabled during Sleep mode
Set and cleared by software.
0: ADC2 clock disabled during Sleep mode
1: ADC2 clock disabled during Sleep mode
Set and cleared by software.
0: ADC1 clock disabled during Sleep mode
1: ADC1 clock disabled during Sleep mode
Reserved, always read as 0.
Set and cleared by software.
0: USART6 clock disabled during Sleep mode
1: USART6 clock enabled during Sleep mode
Set and cleared by software.
0: USART1 clock disabled during Sleep mode
1: USART1 clock enabled during Sleep mode
Reserved, always read as 0.
Set and cleared by software.
0: TIM8 clock disabled during Sleep mode
1: TIM8 clock enabled during Sleep mode
Set and cleared by software.
0: TIM1 clock disabled during Sleep mode
1: TIM1 clock enabled during Sleep mode
RM0033 Rev 8
RM0033