Figure 76. Counter Timing Diagram, Internal Clock Divided By 4; Figure 77. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F205 series Reference Manual

RM0033
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 76. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 77. Counter timing diagram, internal clock divided by N

CK_PSC
20
(UIF)
RM0033 Rev 8
Advanced-control timers (TIM1 and TIM8)
0001 0000
1F 00
0036 0035
MS40510V1
36
MS31187V1
313/1378
375