Figure 223. Usart Block Diagram - ST STM32F205 series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
TX
RX
IrDA
SIR
SW_RX
ENDEC
block
IRDA_OUT
IRDA_IN
RTS
Hardware
flow
CTS
controller
USARTDIV = DIV_Mantissa + (DIV_Fraction / 8 × (2 – OVER8))
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Figure 223. USART block diagram

PWDATA
Write
(CPU or DMA)
Transmit data register (TDR)
Transmit Shift Register
CR3
DMAT DMAR NACK
SCEN
CR2
USART Address
Transmit
control
CR1
RXNE IDLE
TXEIE TCIE TE
IE
IE
USART
interrupt
control
Transmitter
clock
/
[8 x (2 - OVER8)]
SAMPLING
DIVIDER
f
PCLKx(x=1,2)
RM0033 Rev 8
Read
(CPU or DMA)
Receive data register (RDR)
Receive Shift Register
GTPR
GT PSC
CR2
HD
IRLP IREN
LINE
M
UE
Wakeup
unit
CTS LBD
RE RWU SBK
USART_BRR
CR1
OVER8
Transmitter rate
TE
/
USARTDIV
DIV_Mantissa
15
Receiver rate
RE
Conventional baud rate generator
PRDATA
(Data register) DR
SCLK control
STOP[1:0] CKEN CPOL CPHA LBCL
CR1
WAKE PCE PS PEIE
Receiver
clock
Receiver
control
SR
TXE TC RXNE IDLE ORE NF FE
control
DIV_Fraction
4
0
control
RM0033
CK
PE
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