C Trise Register (I2C_Trise) - ST STM32F205 series Reference Manual

RM0033
Bit 14 DUTY: Fm mode duty cycle
Bits 13:12 Reserved, must be kept at reset value
Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum
2
23.6.9 I

C TRISE register (I2C_TRISE)

Address offset: 0x20
Reset value: 0x0002
15 14 13 12
Bits 15:6 Reserved, must be kept at reset value
Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
0: Fm mode t /t = 2
low high
1: Fm mode t /t = 16/9 (see CCR)
low high
Controls the SCL clock in master mode.
Sm mode or SMBus:
T = CCR * T
high PCLK1
T = CCR * T
low PCLK1
Fm mode:
If DUTY = 0:
T = CCR * T
high PCLK1
T = 2 * CCR * T
low PCLK1
If DUTY = 1: (to reach 400 kHz)
T = 9 * CCR * T
high PCLK1
T = 16 * CCR * T
low PCLK1
For instance: in Sm mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
PCLK1
(0x28 <=> 40d x 125 ns = 5000 ns.)
allowed value is 0x01
t = t + t
high r(SCL) w(SCLH)
t = t + t
low f(SCL) w(SCLL)
I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to
the analog noise filter input delay.
The CCR register must be configured only when the I
11 10 9
Reserved
These bits should provide the maximum duration of the SCL feedback loop in master mode.
The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
These bits must be programmed with the maximum SCL rise time given in the I
specification, incremented by 1.
For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t parameter.
HIGH
= 125 ns so CCR must be programmed with 0x28
. See device datasheet for the definitions of parameters.
. See device datasheet for the definitions of parameters.
8 7 6
RM0033 Rev 8
Inter-integrated circuit (I2C) interface
2
C is disabled (PE = 0).
5 4 3 2
TRISE[5:0]
rw rw rw rw
1 0
rw rw
2
C bus
= 125 ns
PCLK1
629/1378
630