Tim9/12 Capture/Compare Register 1 (Timx_Ccr1); Tim9/12 Capture/Compare Register 2 (Timx_Ccr2) - ST STM32F205 series Reference Manual

RM0033
15.4.12

TIM9/12 capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000
15 14 13
rw/ro rw/ro rw/ro rw/ro
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
15.4.13

TIM9/12 capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13
rw/ro rw/ro rw/ro rw/ro
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
12 11 10 9
rw/ro rw/ro rw/ro
If channel CC1 is configured as output:
CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signaled on the OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.
12 11 10 9
rw/ro rw/ro rw/ro
If channel CC2 is configured as output:
CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signalled on the OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.
General-purpose timers (TIM9 to TIM14)
8 7 6
CCR1[15:0]
rw/ro rw/ro rw/ro rw/ro
8 7 6
CCR2[15:0]
rw/ro rw/ro rw/ro rw/ro
RM0033 Rev 8
5 4 3 2
rw/ro rw/ro rw/ro
5 4 3 2
rw/ro rw/ro rw/ro
1 0
rw/ro rw/ro
1 0
rw/ro rw/ro
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