Tim2 Option Register (Tim2_Or); Tim5 Option Register (Tim5_Or) - ST STM32F205 series Reference Manual

General-purpose timers (TIM2 to TIM5)
14.4.19

TIM2 option register (TIM2_OR)

Address offset: 0x50
Reset value: 0x0000
15 14 13
Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:10 ITR1_RMP: Internal trigger 1 remap
Set and cleared by software.
00: TIM8_TRGOUT
01: PTP trigger output is connected to TIM2_ITR1
10: OTG FS SOF is connected to the TIM2_ITR1 input
11: OTG HS SOF is connected to the TIM2_ITR1 input
Bits 9:0 Reserved, must be kept at reset value.
14.4.20

TIM5 option register (TIM5_OR)

Address offset: 0x50
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:6 TI4_RMP: Timer Input 4 remap
Set and cleared by software.
00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table
in the datasheets.
01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes
10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes
11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes.
Wakeup interrupt should be enabled.
Bits 5:0 Reserved, must be kept at reset value.
434/1378
12 11 10 9
ITR1_RMP
rw rw
12 11 10 9
Reserved
8 7 6
8 7 6
TI4_RMP
rw rw
RM0033 Rev 8
5 4 3 2
Reserved
5 4 3 2
Reserved
RM0033
1 0
1 0