Timx Control Register 2 (Timx_Cr2) - ST STM32F205 series Reference Manual

General-purpose timers (TIM2 to TIM5)
14.4.2

TIMx control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TI1S: TI1 selection
Bits 6:4 MMS[2:0]: Master mode selection
Note: The clock of the slave timer and ADC must be enabled prior to receiving events from
Bit 3 CCDS: Capture/compare DMA selection
Bits 2:0 Reserved, must be kept at reset value.
416/1378
12 11 10 9
Reserved
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also Section 13.3.18: Interfacing with Hall sensors
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
the master timer, and must not be changed on-the-fly while triggers are received from
the master timer.
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
8 7 6
TI1S MMS[2:0]
rw rw
RM0033 Rev 8
5 4 3 2
CCDS
rw rw rw
RM0033
1 0
Reserved