Sdi Clock Control Register (Sdio_Clkcr) - ST STM32F205 series Reference Manual

Secure digital input/output interface (SDIO)
26.9.2

SDI clock control register (SDIO_CLKCR)

Address offset: 0x04
Reset value: 0x0000 0000
The SDIO_CLKCR register controls the SDIO_CK output clock.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:15 Reserved, must be kept at reset value
Bit 14 HWFC_EN: HW Flow Control enable
Bit 13 NEGEDGE:SDIO_CK dephasing selection bit
Bits 12:11 WIDBUS: Wide bus mode enable bit
Bit 10 BYPASS: Clock divider bypass enable bit
Bit 9 PWRSAV: Power saving configuration bit
Bit 8 CLKEN: Clock enable bit
Bits 7:0 CLKDIV: Clock divide factor
778/1378
Reserved
0b: HW Flow Control is disabled
1b: HW Flow Control is enabled
When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt
signals, please see SDIO Status register definition in
0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK
1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK
00: Default bus mode: SDIO_D0 used
01: 4-wide bus mode: SDIO_D[3:0] used
10: 8-wide bus mode: SDIO_D[7:0] used
0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the
SDIO_CK output signal.
1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal.
For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting
PWRSAV:
0: SDIO_CK clock is always enabled
1: SDIO_CK is only enabled when the bus is active
0: SDIO_CK is disabled
1: SDIO_CK is enabled
This field defines the divide factor between the input clock (SDIOCLK) and the output clock
(SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].
WID
BUS
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RM0033 Rev 8
9 8 7 6 5 4
CLKDIV
Section 26.9.11.
RM0033
3 2 1 0