Figure 123. Counter Timing Diagram, Internal Clock Divided By 2; Figure 124. Counter Timing Diagram, Internal Clock Divided By 4; Figure 125. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F205 series Reference Manual

General-purpose timers (TIM2 to TIM5)
Timerclock = CK_CNT
Update event (UEV)
Update interrupt flag (UIF)
Timerclock = CK_CNT
Update interrupt flag (UIF)
384/1378

Figure 123. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Counter register
0002
Counter underflow

Figure 124. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 125. Counter timing diagram, internal clock divided by N

CK_INT
Counter register
Counter overflow
Update event (UEV)
0001 0000 0036
0001
20 1F
RM0033 Rev 8
0035 0034 0033
0000 0036
00 36
RM0033
MSv37306V1
0035
MS40511V1
MS37340V1