Timer Input Xor Function; Timers And External Trigger Synchronization; Figure 149. Control Circuit In Reset Mode - ST STM32F205 series Reference Manual

RM0033
14.3.13

Timer input XOR function

The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.
An example of this feature used to interface Hall sensors is given in
14.3.14

Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
•
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don't need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so the user does not need to configure it. The
CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1
register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity
(and detect rising edges only).
•
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
Figure 149
between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Counter clock = CK_CNT = CK_PSC
shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay

Figure 149. Control circuit in reset mode

Counter register
RM0033 Rev 8
General-purpose timers (TIM2 to TIM5)
TI1
UG
32 33 34 35 36
30 31
TIF
Section 13.3.18.
00 01 02 03 00 01 02 03
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