RM0033
2
25.4
I
S functional description
2
25.4.1
I
S general description
The block diagram of the I
MOSI/ SD
MISO
NSS/WS
CK
I2S_ CK
I2SMOD
MCK
The SPI could function as an audio I
setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same
pins, flags and interrupts as the SPI.
2
S is shown in
Figure 264. I
Master control logic
SPI
baud rate generator
MCKOE O DD
RM0033 Rev 8
Figure
264.
2
S block diagram
Address and data bus
Tx buffer
BSY OVR MODF CRC
16-bit
Shift register
LSB first
16-bit
Rx buffer
I2SCFG
I2SSTD
[1:0]
[1:0]
Bidi
Bidi
CRC
mode
OE
EN
LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
First
I 2 S clock generator
I2SDIV[7:0]
2
S interface when the I
Serial peripheral interface (SPI)
CH
UDR
TxE RxNE
SIDE
ERR
Communication
control
CH
CK
DATLEN
LEN
[1:0]
POL
I2S
MOD I2SE
CRC
Rx
DFF
SSM SSI
Next
only
I2SxCLK
2
S capability is enabled (by
ai14748
709/1378
735
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