Pwm Mode; Figure 96. Output Compare Mode, Toggle On Oc1 - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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Advanced-control timers (TIM1 and TIM8)

PWM mode

Pulse Width Modulation mode allows generating a signal with a frequency determined by

the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx

output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. The corresponding preload register must be enabled by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in

upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event

occurs, before starting the counter, the user must initialize all the registers by setting the UG

bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It

can be programmed as active high or active low. OCx output is enabled by a combination of

the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).

Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine

whether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction

of the counter).

The timer is able to generate PWM in edge-aligned mode or center-aligned mode

depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to

In the following example, we consider PWM mode 1. The reference PWM signal

OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the

Write B201h in the CC1R register

Interrupt generated if enabled

RM0033 Rev 8

Match detected on CCR1

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