Figure 118. Counter Timing Diagram, Internal Clock Divided By 4; Figure 119. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F205 series Reference Manual

RM0033 General-purpose timers (TIM2 to TIM5)

Figure 118. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
0035 0036 0000 0001
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37301V1

Figure 119. Counter timing diagram, internal clock divided by N

CK_INT
Timerclock = CK_CNT
Counter register
1F 20 00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37302V1
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