ST STM32F205 series Reference Manual page 12

Contents
13.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 336
13.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
13.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
13.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
13.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
13.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
13.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 344
13.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
13.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
13.4 TIM1 and TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
13.4.8
13.4.9
13.4.10 TIM1 and TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.4.11 TIM1 and TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 367
13.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . 367
13.4.13 TIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . 368
13.4.14 TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . 368
13.4.15 TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . 369
13.4.16 TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . 369
13.4.17 TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . 370
13.4.18 TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . 370
13.4.19 TIM1 and TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . 372
13.4.20 TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . 373
13.4.21 TIM1 and TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
14 General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 376
14.1 TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
14.2 TIM2 to TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
14.3 TIM2 to TIM5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
14.3.1
12/1378
TIM1 and TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 348
TIM1 and TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . 349
TIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . 352
TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 354
TIM1 and TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 356
TIM1 and TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . 357
TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . 359
TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . 362
TIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . 363
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
RM0033 Rev 8
RM0033