Tim10/11/13/14 Register Map; Table 67. Tim10/11/13/14 Register Map And Reset Values - ST STM32F205 series Reference Manual

General-purpose timers (TIM9 to TIM14)
15.5.12

TIM10/11/13/14 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below.
Offset Register
TIMx_CR1
0x00
Reset value
TIMx_SMCR
0x08
Reset value
TIMx_DIER
0x0C
Reset value
TIMx_SR
0x10
Reset value
TIMx_EGR
0x14
Reset value
TIMx_CCMR1
Output compare
mode
Reset value
0x18
TIMx_CCMR1
Input capture
mode
Reset value
0x1C
TIMx_CCER
0x20
Reset value
TIMx_CNT
0x24
Reset value
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value
0x30
TIMx_CCR1
0x34
Reset value
0x38 to
0x4C
482/1378

Table 67. TIM10/11/13/14 register map and reset values

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0 0
0 0
0 0
Reserved
0 0
Reserved
RM0033 Rev 8
CKD
Reserve
[1:0]
d
0 0 0
Reserved
0
OC1M
[2:0]
0 0
IC1F[3:0]
0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
RM0033
0 0 0 0
0 0
0 0
0 0
CC1S
[1:0]
0 0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0 0
0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0