Figure 122. Counter Timing Diagram, Internal Clock Divided By 1 - ST STM32F205 series Reference Manual

RM0033
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn't change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Timerclock = CK_CNT
Counter underflow (cnt_udf)
Update interrupt flag (UIF)

Figure 122. Counter timing diagram, internal clock divided by 1

CK_INT
CNT_EN
Counter register
05
Update event (UEV)
General-purpose timers (TIM2 to TIM5)
04 03 02 01 00
36
RM0033 Rev 8
35 34 33 32 31 30 2F
MSv37305V1
383/1378
436