ST STM32F205 series Reference Manual page 375

RM0033
Table 58. TIM1 and TIM8 register map and reset values (continued)
Offset Register
TIMx_ARR
0x2C
Reset value
TIMx_RCR
0x30
Reset value
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
TIMx_BDTR
0x44
Reset value
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value 0
Refer to
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0 0 0 0 0 0 0 0
Section 3.3: Memory map
Advanced-control timers (TIM1 and TIM8)
1 1
Reserved
0 0
0 0
0 0
0 0
0 0
DMAB[31:0]
0 0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0033 Rev 8
ARR[15:0]
1 1 1 1 1 1 1 1
0 0
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0
LOCK
[1:0]
0 0 0 0 0 0 0 0
DBL[4:0]
Reserved
0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1
REP[7:0]
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
DT[7:0]
0 0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0
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