Configuring The Spi For Half-Duplex Communication; Figure 254. Ti Mode - Master Mode, Continuous Transfer - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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Serial peripheral interface (SPI)

Configuring the SPI for half-duplex communication

The SPI is capable of operating in half-duplex mode in 2 configurations.

1 clock and 1 bidirectional data wire

1 clock and 1 data wire (receive-only or transmit-only)

1 clock and 1 bidirectional data wire (BIDIMODE=1)

This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode

SCK is used for the clock and MOSI in master or MISO in slave mode is used for data

communication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the

SPI_CR1 register. When this bit is 1, the data line is output otherwise it is input.

1 clock and 1 unidirectional data wire (BIDIMODE=0)

In this mode, the application can use the SPI either in transmit-only mode or in receive-only

Transmit-only mode is similar to full-duplex mode (BIDIMODE=0, RXONLY=0): the

data are transmitted on the transmit pin (MOSI in master mode or MISO in slave mode)

and the receive pin (MISO in master mode or MOSI in slave mode) can be used as a

general-purpose IO. In this case, the application just needs to ignore the Rx buffer (if

the data register is read, it does not contain the received value).

In receive-only mode, the application can disable the SPI output function by setting the

RXONLY bit in the SPI_CR1 register. In this case, it frees the transmit IO pin (MOSI in

master mode or MISO in slave mode), so it can be used for other purposes.

To start the communication in receive-only mode, configure and enable the SPI:

In master mode, the communication starts immediately and stops when the SPE bit is

cleared and the current reception stops. There is no need to read the BSY flag in this

mode. It is always set when an SPI communication is ongoing.

In slave mode, the SPI continues to receive as long as the NSS is pulled down (or the

SSI bit is cleared in NSS software mode) and the SCK is running.

sampling trigger sampling trigger

RM0033 Rev 8

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