Table 141. Tx Interface Signal Encoding; Table 142. Rx Interface Signal Encoding - ST STM32F205 series Reference Manual

RM0033
that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV
signal must encompass the frame, starting no later than the SFD field.
•
MII_RX_ER: receive error must be asserted for one or more clock periods
(MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere
in the frame. This error condition must be qualified by MII_RX_DV assertion as
described in
MII_TX_EN
0
1
MII_RX_DV
0
0
0
0
0
1
1
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked
with an external 25 MHz as shown in
quartz to provide this clock, the STM32F20x and STM32F21xmicrocontroller can output this
signal on its MCO pin. In this case, the PLL multiplier has to be configured so as to get the
desired frequency on the MCO pin, from the 25 MHz external quartz.
Ethernet (ETH): media access control (MAC) with DMA controller
Table 142.

Table 141. TX interface signal encoding

MII_TXD[3:0]
0000 through 1111
0000 through 1111

Table 142. RX interface signal encoding

MII_RX_ERR MII_RXD[3:0]
0 0000 through 1111
1
1 0001 through 1101
1
1
0 0000 through 1111
1 0000 through 1111
RM0033 Rev 8
Normal inter-frame
Normal data transmission
Normal inter-frame
0000 Normal inter-frame
Reserved
1110 False carrier indication
1111 Reserved
Normal data reception
Data reception with errors
Figure 318. Instead of using an external 25 MHz
Description
Description
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