ST STM32F205 series Reference Manual page 269

RM0033
Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
Bit 18 TEN2: DAC channel2 trigger enable
Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
Bit 17 BOFF2: DAC channel2 output buffer disable
Bit 16 EN2: DAC channel2 enable
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
Bit 12 DMAEN1: DAC channel1 DMA enable
These bits select the external event used to trigger DAC channel2
000: Timer 6 TRGO event
001: Timer 8 TRGO event
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
This bit is set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are
transferred one APB1 clock cycle later to the DAC_DOR2 register
1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred
three APB1 clock cycles later to the DAC_DOR2 register
DAC_DOR2 register takes only one APB1 clock cycle.
This bit is set and cleared by software to enable/disable DAC channel2 output buffer.
0: DAC channel2 output buffer enabled
1: DAC channel2 output buffer disabled
This bit is set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
RM0033 Rev 8
Digital-to-analog converter (DAC)
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