Figure 74. Counter Timing Diagram, Internal Clock Divided By 1; Figure 75. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F205 series Reference Manual

Advanced-control timers (TIM1 and TIM8)
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
312/1378

Figure 74. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
04
05
(UIF)

Figure 75. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0002
(UIF)
RM0033 Rev 8
03 02 01 00 36 35
0000 0036
0001
RM0033
34 33 32 30 2F
31
MS31184V1
0034 0033
0035
MS31185V1