Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer); Receive Channel N Free Buffer Count Register (Rxnfreebuffer); Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Texas instruments ethernet media access controller (emac)/ management data input/output (mdio) module user's guide
Hide thumbs Also See for TMS320DM646x:
Table of Contents

Advertisement

www.ti.com

5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in
described in
Table
Figure 68. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31
15
LEGEND: R = Read only; WI = Write to increment; -n = value after reset
Table 67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
Bit
Field
31-16
Reserved
15-0
RXnFREEBUF
SPRUEQ6 – December 2007
Submit Documentation Feedback
67.
Value
Description
0
Reserved
0-FFh
Receive free buffer count. These bits contain the count of free buffers available. The
RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
control should be issued against incoming packets (if enabled). This is a write-to-increment field.
This field rolls over to 0 on overflow.
If hardware flow control or QOS is used, the host must initialize this field to the number of available
buffers (one register per channel). The EMAC decrements the associated channel register for each
received frame by the number of buffers in the received frame. The host must write this field with
the number of buffers that have been freed due to host processing.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Reserved
R-0
RXnFREEBUF
WI-0
Figure 68
and
16
0
109

Advertisement

Table of Contents
loading

Table of Contents