Edma - Texas Instruments OMAP-L137 User Manual

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6.9

EDMA

Table 6-14 is the list of EDMA3 Channel Contoller Registers and
Controller registers.
Table 6-14. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
0x01C0 0000
0x01C0 0004
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01C0 0400 - 0x01C0 043C
0x01C0 0440 - 0x01C0 047C
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
0x01C0 1000
0x01C0 1008
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
Copyright © 2008–2014, Texas Instruments Incorporated
ACRONYM
PID Peripheral Identification Register
CCCFG EDMA3CC Configuration Register
GLOBAL REGISTERS
QCHMAP0 QDMA Channel 0 Mapping Register
QCHMAP1 QDMA Channel 1 Mapping Register
QCHMAP2 QDMA Channel 2 Mapping Register
QCHMAP3 QDMA Channel 3 Mapping Register
QCHMAP4 QDMA Channel 4 Mapping Register
QCHMAP5 QDMA Channel 5 Mapping Register
QCHMAP6 QDMA Channel 6 Mapping Register
QCHMAP7 QDMA Channel 7 Mapping Register
DMAQNUM0 DMA Channel Queue Number Register 0
DMAQNUM1 DMA Channel Queue Number Register 1
DMAQNUM2 DMA Channel Queue Number Register 2
DMAQNUM3 DMA Channel Queue Number Register 3
QDMAQNUM QDMA Channel Queue Number Register
QUEPRI Queue Priority Register
EMR Event Missed Register
EMCR Event Missed Clear Register
QEMR QDMA Event Missed Register
QEMCR QDMA Event Missed Clear Register
CCERR EDMA3CC Error Register
CCERRCLR EDMA3CC Error Clear Register
EEVAL Error Evaluate Register
DRAE0 DMA Region Access Enable Register for Region 0
DRAE1 DMA Region Access Enable Register for Region 1
DRAE2 DMA Region Access Enable Register for Region 2
DRAE3 DMA Region Access Enable Register for Region 3
QRAE0 QDMA Region Access Enable Register for Region 0
QRAE1 QDMA Region Access Enable Register for Region 1
QRAE2 QDMA Region Access Enable Register for Region 2
QRAE3 QDMA Region Access Enable Register for Region 3
Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15
Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15
QSTAT0 Queue 0 Status Register
QSTAT1 Queue 1 Status Register
QWMTHRA Queue Watermark Threshold A Register
CCSTAT EDMA3CC Status Register
GLOBAL CHANNEL REGISTERS
ER Event Register
ECR Event Clear Register
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Product Folder Links:
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
Table 6-15 is the list of EDMA3 Transfer
REGISTER DESCRIPTION
(1)
Peripheral Information and Electrical Specifications
OMAP-L137
OMAP-L137
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