Renesas M16C FAMILY series Hardware Manual page 218

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
Table 14.14 STSPSEL Bit Functions
Function
Output of SCL2 and SDA2 pins
Start/stop condition interrupt
request generation timing
(1) In slave mode,
CKDIR is set to "1" (external clock)
STPSEL bit
SCL2
SDA2
(2) In master mode,
CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)
STPSEL bit
SCL2
SDA2
Set STAREQ
to "1" (start)
Figure 14.25 STSPSEL Bit Functions
14.1.3.3 Arbitration
Unmatching of the transmit data and SDA
edge of SCL . Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
2
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to "1" at the
same time unmatching is detected during check, and is cleared to "0" when not detected. In cases
when the ABC bit is set to "1", if unmatching is detected even once during check, the ABT bit is set to
"1" (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to "0" (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to "1" (SDA
occur, in which case the SDA
is set to "1" (unmatching detected).
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
STSPSEL = 0
Output transfer clock and data/
Program with a port determines
how the start condition or stop
condition is output
Start/stop condition are detec-
ted
0
1st 2nd
Start condition detection
interrupt
Set to "1" by Set to "0" by
program program
1st
Start condition detection
interrupt
pin is placed in the high-impedance state at the same time the ABT bit
2
page 198
f o 3 8 5
3rd 4th 5th 6th 7th 8th 9th bit
Stop condition detection
interrupt
2nd 3rd 4th 5th 6th 7th
Set STPREQ
to "1" (start)
pin input data is checked synchronously with the rising
2
output stop enabled) causes arbitration-lost to
2
STSPSEL = 1
The STAREQ, RSTAREQ and
STPREQ bit determine how the
start condition or stop condition is
output
Start/stop condition generation
are completed
Set to "1" by Set to "0" by
program program
8th 9th bit
Stop condition detection
interrupt
14. Serial I/O