Renesas M16C FAMILY series Hardware Manual page 114

M 1 6 C 2 / 8 G o r u p ( M 1 6 C
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
CPU clock
Address
bus
RD signal
WR signal
Data
bus
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address.
CPU clock
Address
CPU use
bus
RD signal
WR signal
Data
bus
(3) When the source read cycle under condition (1) has one wait state inserted
CPU clock
Address
CPU use
bus
RD signal
WR signal
Data
bus
(4) When the source read cycle under condition (2) has one wait state inserted
CPU clock
Address
CPU use
bus
RD signal
WR signal
Data
bus
NOTES:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.5 Transfer Cycles for Source Read
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
CPU use Source
CPU use Source
Source Source + 1
CPU use
Source
Source
CPU use
Source
CPU use
page 94
f o 3 8 5
Dummy
Destination
cycle
Dummy
Destination
cycle
Destination
Source + 1
Destination
Destination
Destination
Source
Source + 1
Source Source + 1
CPU use
CPU use
Dummy
CPU use
cycle
Dummy
CPU use
cycle
Dummy
CPU use
cycle
Dummy
CPU use
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
11. DMAC
CPU use
CPU use