Renesas M16C FAMILY series Hardware Manual page 408

REVISION HISTORY
Rev. Date
Page
64
68
70
71
72
74, 75
75
76
77
83
90
101
110
111
113
114
115
116
117
126
127
128
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
• Figure 9.5 Time Required for Executing Interrupt Sequence note 2 added
• Figure 9.9 Hardware Interrupt Priority Watchdog timer added
______
• 9.6 INT Interrupt modified
______
• 9.7 NMI Interrupt modified
• 9.8 Key Input Interrupt modified
• 9.9 Address Match Interrupt modified
Watchdog Timer
• Figure 10.1 Watchdog Timer Block Diagram and Figure 10.2 WDC Register
and WDTS Register moved
• Figure 10.2 WDC Register and WDTS Register WDC Register: note 1 and
note 2 modified
• 10.2 Cold Start/Warm Start added with Figure 10.3 Cold start/Warm start
Operation Example
DMAC
• note added
• Figure 11.5 Transfer Cycles for Source Read (2) is modified
Timer
• Figure 12.5 TA0 to TA4 Registers, TABSR Register, and UDF Register
Timer Ai Register: note 3 modified
• Figure 12.12 TAiMR Register in Pulse Width Modulation Mode b2 modified,
reserved bit map modified
• Figure 12.23 TBiMR Register in A/D Trigger Mode Note 1 added
• Figure 12.24 TB2SC Register Reserved bit map modified
• Table 12.10 Three-phase Motor Control Timer Function Specifications
Note 2 modified
• Figure 12.26 INVC0 Register Note 1, 3, 5, 6 modified, note 10 deleted
• Figure 12.27 INVC1 Register INV13 bit modified, note 2 added, note 6 modi-
fied
• Figure 12.28 IDB0 Register, IDB1 Register, DTT Register, and ICCTB2 Reg-
ister Values after reset modified, b7-6 in the ICTB2 register modified, reserved
bit map for the ICTB2 register modified
• Figure 12.29 TA1, TA2, TA4, TA11, TA21 and TA41 Register Values after
reset modified, note 6 modified
• Figure 12.30 TB2SC Register Reserved bit map modified
Timer S
• Figure 13.2 G1BT and G1BCR0 Register Values after reset modified,
G1BCR0 Register: note 3 added
• Figure 13.3 G1BCR1 Registers Value after reset modified, note 1 modified
• Figure 13.4 G1BTRR Register modified
Description
Summary
C-3