M
1
6
C
2 /
8
G
o r
u
p
(
M
1
6
C
Interrupt Enable Register 0
b7
b6
b5
b4
b3
b2
Interrupt Enable Register 1
b7
b6
b5
b4
b3
b2
Figure 13.10 G1IE0 and G1IE1 Registers
R
e
. v
2
0 .
0
J
a
. n
3
, 1
2
0
0
7
R
E
J
0
9
B
0
0
4
7
0 -
2
0
0
2 /
, 8
M
1
6
C
2 /
8
) B
Symbol
b1
b0
G1IE0
Bit
Symbol
G1IE00
Interrupt Enable 0, CH0
G1IE01
Interrupt Enable 0, CH1
G1IE02
Interrupt Enable 0, CH2
G1IE03
Interrupt Enable 0, CH3
G1IE04
Interrupt Enable 0, CH4
G1IE05
Interrupt Enable 0, CH5
G1IE06
Interrupt Enable 0, CH6
G1IE07
Interrupt Enable 0, CH7
Symbol
b1
b0
G1IE1
Bit
Symbol
G1IE10
Interrupt Enable 1, CH0
G1IE11
Interrupt Enable 1, CH1
G1IE12
Interrupt Enable 1, CH2
G1IE13
Interrupt Enable 1, CH3
G1IE14
Interrupt Enable 1, CH4
G1IE15
Interrupt Enable 1, CH5
G1IE16
Interrupt Enable 1, CH6
G1IE17
Interrupt Enable 1, CH7
page 145
f o
3
8
5
Address
0331
16
Bit Name
0 : IC/OC interrupt 0 request disable
1 : IC/OC interrupt 0 request enable
Address
0332
16
Bit Name
0 : IC/OC interrupt 1 request disable
1 : IC/OC interrupt 1 request enable
13. Timer S
After Reset
00
16
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
After Reset
00
16
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW